Timing circuits are a core portion of communication systems. Timing circuits are used to generate signals, to decode signals, and to synchronise circuits generating and sending signals and those circuits receiving and decoding those signals. In this fashion, a synchronous communication network proceeds with substantial efficiency of signal rate vs. clock rate.
Phase locked loop circuits are a common solution to synchronising two signals and for frequency synthesis to generate a local oscillation in transceiver circuits. They are used in many different applications, such as in communication and networking systems. For example, microprocessor chips require on-chip clock generation. A phase locked loop enables a precise tracking and.phase locking of a synthesized clock signal to a reference clock signal.
Some prior art phase locked loops operate based on analog algorithms. Such systems are subject to very large phase errors and are heavily influenced by random noise. Because of the analog nature of such systems they are difficult to highly integrate. Also, functions such as a divide by N or edge registration are difficult to implement in an integrated device. Analog systems are also relatively susceptible to loss of phase lock or incapability of obtaining phase lock because of random variations in the system.
Other prior art phase locked loops operate based on digital algorithms. One such phase locked loop (PLL) is identified as MT9042B available from Mitel Corporation and is described in detail in Issue 11 of their publication "Digital Switching & Networking Components". If network synchronization is temporarily disrupted, the MT 9042B provides timing and synchronization signals based on storage techniques. The stored values are determined during synchronized mode when an external reference signal is available and the clock is locked to the external reference signal. When the external reference signal is lost, the stored values are used to attempt to maintain the output clock signal.
Because of the widespread use of wireless communications, it is desirable to reduce power consumption of timing circuits. For example, in U.S. Pat. No. 5,933,031 in the name of Konmo a clock signal generating device is disclosed having an which the phase frequency detector outputs--UP and DOWN--are forcibly set to opposite values. This reduces power consumption when the two signals would otherwise be a same value.
In U.S. Pat. No. 5,783,972 in the name of Nishikawa, another power saving PLL circuit is presented. According to the disclosure, a charge pump circuit is provided with a plurality of different current sources for each of the UP and DOWN output ports. This allows for lower power operation of the charge pump when variations in phase frequency are small. Since this is the most common occurrence in a stable communication system, the overall PLL power consumption is reduced. That said, the proposed circuit requires several current sources for each output port and, as such, is more complicated than previously used circuits.
In U.S. Pat. No. 5,598,405 in the name of Hirose, another power saving circuit is presented. Here the phase control loop is only "turned on" preceding each transmission time slot and each reception timeslot. As such, when only a few of several time slots are used, the phase control loop is enabled less than all the time. This results in power savings.
It is an object of the present invention to provide a PLL for consuming less power than a simple prior art PLL circuit while providing similar functionality.